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RE: 64 Bit Base Address Register
You are correct: A 64-bit BAR is created by "concatenating" two consecutive 32-bit registers together. The one at the lower address is the low 32-bits and include the indicator fields. The one at the next higher address is the upper 32-bits.
And Yes, if a device has all 64-bit BARs, then it can only have 3 of them.
If you want more, then you could have a multi-function device, where one function contains the first 3 64-bit BARs and the second function has the next 3 64-bit BARs and the the third function has the next 3 64-bit BARs, etc....
Note: I speak for myself, not for Brocade.
From: Olaf Reichenbaecher [mailto:Olaf.Reichenbaecher@sci-worx.com]
Sent: Thursday, November 02, 2000 6:07 AM
Subject: 64 Bit Base Address Register
i am currently dealing with the issue to design a 32-bit PCI
interface module which supports 64-bit addressing (DAC).
i am wondering what the topology of the BARs in the CS header
assuming an address space of 2GB or less which may be located
anywhere in the 64-bit address space, the BAR pointing to that
address space has to implement 33 or more (dependent on the
actual size) read-write bits.
is this accomplished by "concatenating" 2 subsequent 32-bit BARs
in the CS header? which one would be the upper part (bits 63:32),
which one the lower (bits 31:0). which of the "concatenated"
BARs features the indicator fields (prefetch/type/mem-io)?
does that mean a PCI function may only claim a maximum of
3 base address spaces if all of them may be located
anywhere in the 64-bit address space?
although i scanned through the archive and found a number
of valuable information this issue is quite unclear to me.
even the spec was not of much help.
can someone please shade some light on this? any help
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