Re: Real-world disconnects

[Gérard Roudier <groudier@club-internet.fr>]

On Thu, 2 Nov 2000, Marco Brambilla wrote:

> Hi Gerard,
> 
> > The MWI may be useful for cache-able targets that gain advantage on full
> > cache line invalidations. Even if it has cache, a target may be unable to
> > gain advantage of MWI. We can also imagine targets that do invalidate a
> > full cacheline at a time on MWI, but can also `disconnect' inside a cache
> > line and maintain coherency for the partially transmitted cache line.
> 
> I think MWI is especially useful when you're a master and want to move
> data to host RAM without being interrupted.

Hmmm.... It may work like that with some target, but assuming so does not
seem sane to me.

> But of course no target (the mem controller in this case) is obliged to
> actually implement MWI, so it can as well alias it to the "normal"
> write, as we all know.

Indeed.

And this does not prevent it from accepting large WRITE transactions, in
theory. If aliasing MWI to MW makes it disconnect on each cache line, such
a memory controller can be stated as poor. But we can imagine some
implementing some sophisticated buffering (double should be enough) that
allows it to stream just fine on large MW (real or aliased from MWI),
transactions. In this latter case, I donnot see any problems, if it just
don't care about cache line boundaries, given that expected performances
are achieved with MW semantic.

> > This let me say that a cache-able target disconnecting a MWI on a partial
> > cacheline must be considered as a quite normal situation by a PCI
> > initiator, even if it may well be unusual in practice.
> 
> Yes. For sure one situation your master must be aware of (and if it is
> not, then it is broken ;)
> 
> > Marco's posting does not seem to address any PCI controller flaw.
> 
> Yap. That's right.
> 
> This behaviour is perfectly compliant with the PCI standard.
> 
> My question comes from profiling issues: I have a master device, which
> moves to and from RAM at least 4 channels of data + 2 of control.
> 
> This means that you have to identify a good priority scheme and verify
> the impact of bus behaviour in the drivers.
> 
> Not that I expect a MWI disconnect to be of much impact, this is most
> for the sake ok information.
> 
> But if you think of a highly loaded system, if the mem controller
> disconnects after few (2/3) data phases, this can have an impact in
> system performances, especially if the latency is high on the bus.

In order to honour latency requirement on highly loaded systems, the right
trade-off should be to shorten transactions. A single master has no
knowledge about such requirement. I want to say that PCI chip designers
should be careful about not wasting PCI cycles when PCI transactions get
short due to disconnections or short latency timer having been configured,   
(i.e. they should think about supporting fast back to back transactions
for example), instead of whining about being early disconnected by
targets.

Salut,
  Gérard.

> Ciao, Marco.
> 
> -- 
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>  Marco BRAMBILLA   
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