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Re: Real-world disconnects

groudier@club-internet.fr wrote:

> > I think MWI is especially useful when you're a master and want to move
> > data to host RAM without being interrupted.
> Hmmm.... It may work like that with some target, but assuming so does not
> seem sane to me.

Ok, let's reword:

MWI is especially useful when you want to tell to the system that you
would like to not be interrupted (and you guarantee the number of data

> And this does not prevent it from accepting large WRITE transactions, in
> theory. If aliasing MWI to MW makes it disconnect on each cache line, such
> a memory controller can be stated as poor. 

If it does aliasing it can disconnect wherever it wants.

> In order to honour latency requirement on highly loaded systems, the right
> trade-off should be to shorten transactions. A single master has no
> knowledge about such requirement. I want to say that PCI chip designers
> should be careful about not wasting PCI cycles when PCI transactions get
> short due to disconnections or short latency timer having been configured,
> (i.e. they should think about supporting fast back to back transactions
> for example), instead of whining about being early disconnected by
> targets.

This is close to the contrary of what Intel is saying in an application
They recommend using bursts as long as possible, using the advanced
memory commands (MWI, MRL, MRM).

So the trick is trying to use transactions as long as possible, because
where you lose efficiency is the rearbitration / transaction setup.

It is to be said, on the other hand, that this kind of problems will
only be felt by high-throughput devices.

In any case I was not complaining, whining or anything :)

I was just asking if anyone knows how ACTUAL chipsets (not generic
targets) behave, but no one seems to have that particular information.

Ciao, Marco.

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