RE: timing question

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

>                I want to know how PLL can be used to reduce clock
> insertion
> delay.(if your statement is infering the same thing offcource!).
 
A PLL as a clock repeater can be configured to have virtually any "delay",
positive or negative.  It's all a matter of choosing the delay in the
feedback path.

Find some basic tutorials on using a PLL as a clock repeater.

For example, if the PLL enforces an exact zero time difference between its
Reference and Feedback inputs (an ideal which is never quite achievable),
and the Feedback is taken from the output of the clock tree plus an
additional (say) 1ns of delay, then the output of the clock tree will be 1ns
earlier than the Reference input.  This is an effective PLL + clock tree
delay of negative 1ns.

A PLL can not be used in 0-33MHz mode (unless this is for a dedicated system
only).

Andy