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RE: timing question



>  The timing
> on the pads is as follows -
> CLK->Q + PCI66DGZ = Total
> 0.60   + 4.50     = 5.10 ns
 
Make sure that these are measured with the correct test loads, according to
the 66MHz PCI Specs.  If their library delays used something like a 50pF
load, that would give you incorrect timing data.

Sometimes, and only when you have enough control over your ASIC, you can
pick off an "early" clock from the clock tree and use that to drive your
output registers.  That might improve their Tval timing.  But watch out for
other timing hazards elsewhere if you do this.

Andy