Re: timing question

[Neal Palmer <neal@dinigroup.com>]

Sachin,

  If your problem is worse than theirs, then I highly suggest that you
don't attempt to use a PLL, and instead have somebody fix your IO cells to
make them faster.  You will probably spend less time, money, and get a
smaller working chip the first try if you don't use a PLL.  Just my humble
opinion.

-- Neal

On Wed, 8 Nov 2000, Sachin Kadu wrote:

> Hi Vijay,
>               We are facing the same problem. In our case clock insertion
> delay is more than yours.
>                You are saying "Since we do not use a PLL and since ....".
>                I want to know how PLL can be used to reduce clock insertion
> delay.(if your statement is infering the same thing offcource!).
>                                    Thanks in advance,
>                                        Sachin
> 
> ----- Original Message -----
> From: "Vijay Chougule (by way of Daniel Weaver <dan.weaver@znyx.com>)"
> <vchougule@yahoo.com>
> To: <pci-sig@znyx.com>
> Sent: Tuesday, 07 November, 2000 11:24 PM
> Subject: timing question
> 
> 
> > Hi All,
> >
> > I am designing a 64 bit 66 MHz PCI card. I have a
> > question about the PCI output timing.
> >
> > We are using the TSMC 0.18 micron process (segmented
> > TSMC16K_Conservatative wire load model) and the IO
> > libraries are provided by Artisan. I am using the
> > bidirectional pad PCI66DGZ for my PCI IOs. For PCI
> > clock I am using PDIDGZ. All my outputs are registers
> > and the signals controlling the PADs are also
> > registered.
> > After synthesizing the core and linking the PADS I am
> > getting timing violations on the outputs. The timing
> > on the pads is as follows -
> > CLK->Q + PCI66DGZ = Total
> > 0.60   + 4.50     = 5.10 ns
> >
> > Since we do not use a PLL and since there is a clock
> > tree delay after I get the clock from the PADS, I am
> > adding a timing of 2.2 ns (accounting for the delays
> > dur to clock tree insertion). So my outputs will be
> > valid after a total of 7.30 ns (5.10 + 2.20) which is
> > clearly a violation of timing for 66 Mhz PCI.
> > I think the PAD delay is too much.
> >
> > Can anyone share their experience of using the above
> > Artisan libraries ? Has anyone experienced teh above
> > problems ? OR What should be the maximum PAD delays
> > for satisfying the timing from registered outpur
> > signals ?
> >
> > OR am I doing something wrong in my calculations ?
> >
> > I appreciate your replies.
> >
> > Thank you,
> > Vijay
> >
> >
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> 

-- Neal Palmer

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