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Re: timing question
> Make sure that these are measured with the correct test loads, according to
> the 66MHz PCI Specs. If their library delays used something like a 50pF
> load, that would give you incorrect timing data.
it might be a tricky task for an ASIC/library vendor to model the
correct test loads (capacitive AND resistive). as far as i know they
just go with modelling the capacitve loads. recently we had a
discussion with an ASIC vendor regarding this issue. they calculated
PAD delay with 50 pF by default and we wanted then to do it with
PCI test loads (10 pF/25 Ohms). their standard delay calculator was
not able to model the resitive part. in order to prove correctness
when just using only the 10 pF part they performed a spice simulation
for the PADs with 10 pF and 25 Ohms. as expected the delay calculation
with just 10 pF was way to optimistic. but, surprisingly, the
PAD delay calcuted with 10 pF/25 Ohms was even worse than the PAD
delay calculated with just 50 pF.
so although the timing with 50 pF load is not correct is might be
closer than any the ASIC/library vendor is able to provide with
their standrad approach.
but nevertheless it is always a good idea to double check on this.
Senior Design Engineer
Garbsener Landstr. 10
Tel +49 (0)511 277-1432
Fax +49 (0)511 277-2410