Re: timing question

[Steve Blightman <steve@alacritech.com>]

We have been seeing some of the same problems too.  We have noticed that
there are differences between the worst case  IO library and the
Standard cell core library.  The IO library, characterized as "WCCOM" is
characterized at 3.0 volt, nominal process of 1.188.  The Standard cell
library is characterized as "slow" at 1.62 volt, nominal process of 1.
Unfortunately Synopsys does not allow us to synthesize at mixed
operating conditions, so we synthesize at "slow".  This means that the
IO cells are further derated, and you have the excessive unreal delays.
We believe at the moment that we can work around this problem by editing
in the "slow" operating condition into the IO library.  Of course, I
don't know whether this is your problem too, but I hope this helps.


"Vijay Chougule (by way of Daniel Weaver )" wrote:

> Hi All,
>
> I am designing a 64 bit 66 MHz PCI card. I have a
> question about the PCI output timing.
>
> We are using the TSMC 0.18 micron process (segmented
> TSMC16K_Conservatative wire load model) and the IO
> libraries are provided by Artisan. I am using the
> bidirectional pad PCI66DGZ for my PCI IOs. For PCI
> clock I am using PDIDGZ. All my outputs are registers
> and the signals controlling the PADs are also
> registered.
> After synthesizing the core and linking the PADS I am
> getting timing violations on the outputs. The timing
> on the pads is as follows -
> CLK->Q + PCI66DGZ = Total
> 0.60   + 4.50     = 5.10 ns
>
> Since we do not use a PLL and since there is a clock
> tree delay after I get the clock from the PADS, I am
> adding a timing of 2.2 ns (accounting for the delays
> dur to clock tree insertion). So my outputs will be
> valid after a total of 7.30 ns (5.10 + 2.20) which is
> clearly a violation of timing for 66 Mhz PCI.
> I think the PAD delay is too much.
>
> Can anyone share their experience of using the above
> Artisan libraries ? Has anyone experienced teh above
> problems ? OR What should be the maximum PAD delays
> for satisfying the timing from registered outpur
> signals ?
>
> OR am I doing something wrong in my calculations ?
>
> I appreciate your replies.
>
> Thank you,
> Vijay
>
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