RE: PCI clock

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> regarding the PCI clock
> can U specify the clock jitter (especially on the rising) ??
 
For 33MHz PCI, the clock jitter can be anything; it has no limit.  Clocks
can start and stop and change on any cycle, as long as the minimum cycle
time (30.000ns) is not violated.  On most PC models, it is a lot less.  But
if you want to know the maximum jitter you might find in any PCI system,
there is no limit.

For 66MHz PCI, there are some additional specifications with respect to
clock frequency modulation (for so-called "spread spectrum" EMI reduction).
These specifications (see Table 7-3 in the PCI spec, revision 2.2) are in
the frequency domain, not the time domain, because of their effect on
downstream PLLs.  If I remember right, the jitter from one cycle to the next
amounts to less than 0.1ns, but the jitter from one cycle to another that is
several cycles later, would be much greater, as expected for a (relatively)
slow frequency modulation.  It's been a while since I looked at this stuff.