Relates to cache line and MWI

[Ajit Khaparde <akhaparde@platysindia.com>]

PCI designers,
Thanks for the response to the earlier query I had put here.
Now I want some clarification reg:-

When a MWI command is used and if the system finds that the cache line is marked "dirty", is it not the responsibility of the system to transfer the dirtied cache line to system memory before writing the I/O data to system memory?

In any case, how is the change made by ane device(say I/O or Processor) to a cache line preserved when one write transaction is followed by another with both writing full cache line?

Regards,
Thanks in advance,
Ajit Khaparde

Platys Communications (India) Pvt. Ltd.

ajitkhaparde@yahoo.com
akhaparde@platysindia.com


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