Spread Spectrum PCI clock

[Ted Firlit <firlit@utmc.aeroflex.com>]

I am currently trying to fix a PCI card design on which I used a
Motorola
MPC931 PLL to multiply the 33Mhz clock to 100Mhz, and also provide 33Mhz
to 2 inputs on the PCI interface device.  This works fine in
motherboards without
spread spectrum, but does not lock proper phase with spread spectrum. 
Motorola FAE's are currently trying to determine an input spec for me
(modulation freq and % of freq deviation(modulation width)).

I noticed that the PCI 2.2 spec addresses SSC, but have just ordered it
so I don't yet know the details. 

I also noticed Cypress has "spread aware" PLL's, but no specs on the
modulation freq or width of the input clock.  Does anyone have
information on the limits of these parameters in current PC
motherboards?  I see that the ICS9148 clock generation part will allow
selection of up to 4% modulation width-- is this being selected in
motherboards?

What downstream PLL's are being successfully used with SSC?  Any use of
66Mhz to 100Mhz freq multipliers besides the Motorola 931 and 972?

Thanks for any info,

Ted Firlit
firlit@utmc.aeroflex.com
UTMC Microelectronic Systems
Colorado Springs, CO 80907