PCI clock distribution

[Ted Firlit <firlit@utmc.aeroflex.com>]

Hello all,

Since the PCI spec requires only one load on the PCI-CLK signal, has
anyone found a buffering device which would allow multiple destinations
on a target card?  Requirements would be:

 - up to 66Mhz input clock
 - 5V and 3.3V input tolerance
 - 3.3V output voltage
 - 12pf max input capacitance, output drives >= 20pf
 - little delay through device (~500 psec)
 - passes Spread Spectrum with low skew

Thanks for any help you may have.

Ted
-- 
Ted Firlit		      		(719) 594-8138
Senior Design Engineer
UTMC Microelectronics Systems
4350 Centennial Blvd., MS 1004
Colorado Springs, CO 80907