Re: REQ64# <-> ACK64# - handshake-mechanism in performing a single 64-bit (Write)-Transfer

["Weng Tianxiang" <wtx@umem.com>]

Hi,
1. You have to assert FRAME# and nREQ64 to try to do a 64-bit transaction.
2. If Target has no response from neither DEVSEL# nor STOP# asserted within
4 clock since FRAME# is asserted, Master has to do a Master abortion: do
last data cycle: FRAME# deasserted and IRDY# asserted and deasserted both
and release PCI bus if no nGNT is granted.
3. Other situations are descripted in PCI 2.2 p.51.

Weng Tianxiang
Micro Memory Inc.
9540 Vassar Av.
Chatsworth, CA 91311
Phone: 818-998-0070, Fax: 818-998-4459


----- Original Message -----
From: Kirchmayer Markus <markus.kirchmayer@mchr2.siemens.de>
To: <pci-sig@znyx.com>
Sent: Wednesday, December 06, 2000 1:11 AM
Subject: REQ64# <-> ACK64# - handshake-mechanism in performing a single
64-bit (Write)-Transfer


> Hi,
>
> We have designed a PCI card with a Lucent-PCI-Interface Controller
> (OR3LP26). Unfortunately we have a problem in a
> 64bit PCI environment and at the moment we don't know if the OR3LP26 or
the
> PCI Host-Bridge causes the problem. Also the
> PCI spec. seems to be not very clearly at that point (at least we haven't
> found it).
> The question is now, if it is necessary that the master keeps FRAME#
> and REQ64# asserted until the target responses with DEVSEL# asserted and
> ACK64# asserted (or not asserted in case of
> a 32bit-target) or is it ok to deassert FRAME# and REQ64# as soon as the
> master is ready to signal that it is in the final (single)
> data phase (IRDY# asserted, FRAME# and REQ64# deasserted). This would
result
> in max. 2 TW-Cycles, in which neither REQ64#
> nor ACK64# are asserted. The attached text file shows a trace of this
> situation.
>
> Any comments would be appreciated. Thank you very much.
>
> Regards,
>
> Markus Kirchmayer
>
>
>  <<psa8_64_short.TXT>>
>
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