Fwd: pci bandwidth calculations

[Alan Deikman <Alan.Deikman@znyx.com>]

>From: Tom Curran <tom_curran@memecdesign.com>
>Subject: pci bandwidth calculations
>
>I was wondering if anyone knows of an app note or white paper that discusses
>how to effectively calculate FIFO depths for any given PCI bandwidth
>requirement?

The correct FIFO depth is a function that is more dependent
on the maximum latency of the common bus (in this case PCI)
than it is of bandwidth, particularly where the nominal data
rate of the common bus is large compared to the peripheral
bus (which you did not specify.)

For example, assuming you have a 100 Mbit/s incoming serial
stream for a peripheral, and the PCI bus is clocked such
that its data rate is approximately 1,000 Mbit/s.  The FIFO for
incoming data should be large enough to store at least 100Mbits
times  the largest possible latency.  If that is 40 microseconds
then (if my slipstick is working) you need 4,000 bits of
FIFO.  Note that the bandwidth of the PCI bus is not a
significant variable.

If the peripheral and common bus are close in bandwidth,
a differential equation would be needed to solve it precisely.
Most engineers I know wouldn't bother; just double the amount
from the formula above, run it on the bench, and call it a day.

If the peripheral bus is faster than the common bus, then
no amount of FIFO will save you, unless you have some sort of
flow control on the peripheral bus.

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