Re: very slow response of memory read with VIA KT133 chipset

["Weng Tianxiang" <wtx@umem.com>]

Hi,
I have been designing a PCI interface with SDRAM memory control functions.

My SDRAM design exploited every clock to achieve 14 clock read response time
starting with FRAME# asserted. If this design were moved to a motherboard, 2
clocks might be saved further. With above situation in mind, I think 18
clock read resonse time is the one of fastest design. The reason is the
memory you have access is on the other side of PCI bus, that means
additional 2 or more clocks are needed for bridge to receive read command on
one side of PCI and transfer the command to other side of PCI and vice verse
for data transfer. 16 clocks PCI specification is not violated in my design,
but a Master may see a longer delay if a request is issued from other side
of PCI bus.  45 clocks read response can be blamed to motherboard chip
design or combination of motherboard chip and memory control functions.

Weng Tianxiang
Micro Memory Inc.
9540 Vassar Av.
Chatsworth, CA 91311
Phone: 818-998-0070, Fax: 818-998-4459


----- Original Message -----
From: <yang.can.mei@philips.com>
To: <pci-sig@znyx.com>
Sent: Tuesday, January 02, 2001 12:33 AM
Subject: very slow response of memory read with VIA KT133 chipset


> Hi PCI experts,
>
> Could you guys give a little light on following problem.
>
> We are testing our PCI device. We got some problems with PCI interface of
KT133 chipset and we couldn't find out The system is:
>
> CPU: AMD Athelon/ Duron
> Motherboard:K7T Pro2 from MSI and KT7-RAID from ABIT
> Chipset: KT133 chipset(VT8363) and SouthBridge VT82C686A from VIA
> OS: Win98SE
>
> We found:
> . The master memory write of our PCI device works fine, no wait cycle(I
guess this is because all the write were posted in VT8363)
> . But each master memory read gets to wait an abnormally long time to
obtain response from target(I guess this is due to VT8363, not the real
memory). The wait cycle are around 18 for MSI motherboard and 45 PCI cycles
for ABIT motherboard. In both cases,
> the waiting time is longer than defined value in PCI specification.
> . We changed different memory, the problem still exists.
> . We tested different PCI device of same class, the waiting time is
basically same, but the other PCI device work,
> . More seriously,our PCI device, didn't work. The target(memory
controller) didn't reply with any data after it asserted DEVSEL(that means
memory controller has finished decode of command address) to master (our
device), but didn't give anything
> thereafter. Then our device must die because our PCI device saw DEVSEL
from target. If our PCI master didn't see DEVSEL asserted by target, the
master could issue a master abort.
>
> From our understanding of PCI spec., memory read should be very fast from
PCI viewpoint, it is easy to meet the latency requirement for most PCI
bridge designs. So our question is,
> Have you met the same problem? What is the rootcause of this slow response
of memory read?
>
> Thanks in advance
>
> Paul Yang C.M.
> Philips Semiconductors
>
>
>