RE: 21154 Bridge SCLK Power-up Errata

["Olaf Birkeland" <Olaf.Birkeland@fast.no>]

> -----Original Message-----
> From: Mike Dini [mailto:mdini@dinigroup.com]
> Sent: Thursday, December 28, 2000 02:00
> To: pci-sig@znyx.com
> Subject: 21154 Bridge SCLK Power-up Errata
>
>
> The 21154 from DEC/Intel has a power-up errata on the secondary clocks
[snip]
> Has anybody actually found that this part will not power-up correctly and
> that the errata is real?
>
> Any other ways to get around this errata (if it really happens)?
>

I've contacted Intel, and got precice and accurate response from their
support site within two buisiness hours ;-) The errate is real, but only
occurs during "hot" power cycling, i.e. a power cycle where internal nodes
haven't had time to fully discharge.

They had a new rev. in the pipeline (-AD/BD) that should be available in
early Q2 that should fix this.

Regards,
- Olaf