How to trade-off between a long timeout of TRDY response and system bandwidth holdingup time?

[yang.can.mei@philips.com]

Hi PCI Guru:

I'm testing my PCI device with different motherboard which has different HostBrdige or PCI bridge. My OS is Win98SE, my device is  USB 2.0 Host Controller. I made a PCI-based FPGA board. PCI core is downloaded in one of three FPGA EP20KE400BC-1 from 
ALTERA. This is a multiple function solution, two of them are USB OHCI core, the other one is USB EHCI. Every function has PCI master and target functionality.

As you know, PCI master has a latency timer to avoid from consuming too much PCI time for the same PCI transaction. But so many PCI devices(accurately PCI systems, not an individual PCI device)  are not PCI-specificaiton compliant 100%, so it is 
reasonable to implement an extra timeout in configuration space to define how long the master can wait for a target to response, then it just time out from waiting state and give up the PCI bus. That makes a lot senses in our USB2 Host Controller, 
because, one of data transfer type(High Speed ISO high bandwidth ISO transfer) may need consume 1/2 of whole PCI bandwidth. So our implementation is to setup a TRDY waiting timeout in Congfiguration space (offset 0x40) to limit the waiting time

Now the problem is :

When my PCI master(any USB host) tried to read some system memory locations, the target (HostBrdiges like KT8363 of VIA, 815Eof Intel) responses to the PCI master very slowly sometimes(I don't know the reason), farther away from PCI specification.  So 
the PCI master would timeout the memory read. This PCI transaction just failed, and system can do something else(not related to this PCI device)

But if we disable this timeout as done in general PCI device, this kind of PCI transaction may be finished finally anyway, but it consumed too much bandwidth here, that would affect other device or function (EHCI) operation definietely.

So either I don't implement this TRDY timeout to limit this device bandwidth consumption or letting it go but affecting other bandwidth-senstive device like USB2 EHCI device. 

Anybody out there can share me some ideas to solve this problem? And what about the opinion of PCI-SIG about these kind of problems?

Is my description clear?

Paul Yang C.M.
Philips Semiconductors, Asia Product Innovation Centre
620A, Lorong 1 Toa Payoh TP3 Level 3
Singapore 319762

Tel: (65)  3517373
Fax: (65) 2591287
Email: Yang.Can.Mei@philips.com