Any PCI specs violation?

["Weng Tianxiang" <wtx@umem.com>]

Hi,

I have been designing PCI 66MHz/64-bit core. The following is a code excerpt. I want to know if the following equation violates any PCI specs:

 

  case MState is
       when MIdle_S =>
            -- device is not disconnected and is granted PCI bus
            -- here nFRAME can be replaced by nFrame_R
            if(MEnableMemory and nGNT = '0' and nFrame_R = '1' and nIRDY = '1') then
                 -- if requested by Master module
                 if(nReq_O = '0') then
                    ...

 

1. This is a Master state machine first state: Master idle state;

2. nFrame_R is registered value of nFRAME, 1 clock later than nFRAME;

3. If nFrame_R above is replaced by nFRAME, there is no any problem;

4. The reason to replace nFRAME with nFrame_S is to reduce nFRAME fanout as much as possible;

 

Is there any possibility that the above replacement causes problem?

 

Thank you.

 

Weng Tianxiang
Micro Memory Inc.
9540 Vassar Av.
Chatsworth, CA 91311
Phone: 818-998-0070, Fax: 818-998-4459