Re: Any PCI specs violation?

[Olaf Reichenbaecher <Olaf.Reichenbaecher@sci-worx.com>]

hi there,

> I have been designing PCI 66MHz/64-bit core. The following is a code
> excerpt. I want to know if the following equation violates any PCI
> specs:
> 
>   case MState is
>        when MIdle_S =>
>             -- device is not disconnected and is granted PCI bus
>             -- here nFRAME can be replaced by nFrame_R
>             if(MEnableMemory and nGNT = '0' and nFrame_R = '1' and
> nIRDY = '1') then
>                  -- if requested by Master module
>                  if(nReq_O = '0') then
>                     ...
> 
> 1. This is a Master state machine first state: Master idle state;
> 2. nFrame_R is registered value of nFRAME, 1 clock later than nFRAME;
> 3. If nFrame_R above is replaced by nFRAME, there is no any problem;
> 4. The reason to replace nFRAME with nFrame_S is to reduce nFRAME
> fanout as much as possible;
> 
> Is there any possibility that the above replacement causes problem?

your master state machine is going to detect the PCI bus' idle state
before starting any activity on the bus. by the time IRDY# has gone
inactive from some previous transaction FRAME# has already been
deasserted at least one cycle before. so far no problem.

i have constructed the following signal scheme. although not very
likely (?) the PCI spec permits it:
suppose agent B is your master device and agent A is another one.
the arbiter serves agent B with a higher priority than agent A.
since the arbiter is allowed to deassert GNT# at any time while
FRAME# is deasserted in order to serve a higher priority master,
it removes the GNT# from A and gives it to B in cycle 2. agent A
asserts FRAME# in the same cycle since it has seen it's GNT#. in
cycle 3 your device (agent B) sees it's GNT# asserted. IRDY# is not
yet asserted and the registered FRAME# is still in inactive state
as well, so your device asserts FRAME# in order to start a transaction
and this way interferes with the transction of agent A.
            __    __    __    __    __
CLK       _| 1|__| 2|__| 3|__| 4|__| 5|_
                   ___________________
GNT#(A)   ________|
          ________             _______
GNT#(B)           |___________|
          ________       _____________
FRAME#(A)         |_____|_____________
          ______________
IRDY#(A)                |_____________
          ______________       _______
FRAME#(B)               |_____|_______
          ____________________
IRDY#(B)                      |_______

i hope my example is clear enough in order to reveal the potential
functional problem. being a PCI core designer on my own i don't
think you might be able to reduce the fanout on PCI bus signals
significantly by using the registered ones instead at such specific
points.

cheers!

  olaf
-- 
Olaf Reichenbaecher
Senior Design Engineer
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