RE: Any PCI specs violation?

["Francois Barlow" <fbarlow@matrox.com>]

Hi,

>             __    __    __    __    __
> CLK       _| 1|__| 2|__| 3|__| 4|__| 5|_
>                    ___________________
> GNT#(A)   ________|
>           ________             _______
> GNT#(B)           |___________|
>           ________       _____________
> FRAME#(A)         |_____|_____________
>           ______________
> IRDY#(A)                |_____________
>           ______________       _______
> FRAME#(B)               |_____|_______
>           ____________________
> IRDY#(B)                      |_______
>

The situation described by your waveform is not accurate,
because the PCI spec says that "a GNT# can be deasserted
coincident with another GNT# being asserted if the bus is
not in the IDLE state" (PCI spec rev 2.2 page 254, Arbitration
section point 23-b).

In the situation above, one clock delay is required
between GNT#(A) deassertion and GNT#(B) assertion because
the bus was IDLE when the arbiter took the decision to
remove GNT#(A) signal.

Using the registered version of FRAME# to know the state
of the bus is possible only if you can insure that no
fast-back-to-back cycle are perform on the PCI bus.
If fast-back-to-back cycles are supported, the problem
would appear in the following situation, where a fast-
back-to-back cycle is performed by master "A" (where
master "B" is still your PCI master device):

            __    __    __    __    __
CLK       _| 1|__| 2|__| 3|__| 4|__| 5|_
                   _____________________
GNT#(A)   ________|
          ________
GNT#(B)           |_____________________
             _____       _______________
FRAME#(A) __|     |_____|_______________
                   _____
IRDY#(A)  ________|     |_______________
          ______________       _________
FRAME#(B)               |_____|_________
          ____________________
IRDY#(B)                      |_________


During cycle 1, Master "A" was in the last data phase
of its transaction and is allowed to initiate a fast-back-
to-back cycle on cycle 2 because GNT#(A) was asserted
during cycle 1.  However, during cycle 1 the arbiter sees
the bus busy and it is then allowed to change both GNT#
signals simultaneously at cycle 2.  During cycle 2, if
master "B" is not able to see that the bus is busy (it'll
be the case using a registered version of FRAME#), master
"B" transaction will interfere with master "A" transaction.

François.

**********************************
François Barlow
Asic Design Leader
Matrox electronic systems
Imaging department
tel: 514-685-7230 x2280
fax: 514-822-6110
email: fbarlow@matrox.com
**********************************


-----Original Message-----
From: Olaf Reichenbaecher [mailto:Olaf.Reichenbaecher@sci-worx.com]
Sent: Friday, January 12, 2001 3:07 AM
To: wtx@umem.com
Cc: pci-sig@znyx.com
Subject: Re: Any PCI specs violation?


hi there,

> I have been designing PCI 66MHz/64-bit core. The following is a code
> excerpt. I want to know if the following equation violates any PCI
> specs:
>
>   case MState is
>        when MIdle_S =>
>             -- device is not disconnected and is granted PCI bus
>             -- here nFRAME can be replaced by nFrame_R
>             if(MEnableMemory and nGNT = '0' and nFrame_R = '1' and
> nIRDY = '1') then
>                  -- if requested by Master module
>                  if(nReq_O = '0') then
>                     ...
>
> 1. This is a Master state machine first state: Master idle state;
> 2. nFrame_R is registered value of nFRAME, 1 clock later than nFRAME;
> 3. If nFrame_R above is replaced by nFRAME, there is no any problem;
> 4. The reason to replace nFRAME with nFrame_S is to reduce nFRAME
> fanout as much as possible;
>
> Is there any possibility that the above replacement causes problem?

your master state machine is going to detect the PCI bus' idle state
before starting any activity on the bus. by the time IRDY# has gone
inactive from some previous transaction FRAME# has already been
deasserted at least one cycle before. so far no problem.

i have constructed the following signal scheme. although not very
likely (?) the PCI spec permits it:
suppose agent B is your master device and agent A is another one.
the arbiter serves agent B with a higher priority than agent A.
since the arbiter is allowed to deassert GNT# at any time while
FRAME# is deasserted in order to serve a higher priority master,
it removes the GNT# from A and gives it to B in cycle 2. agent A
asserts FRAME# in the same cycle since it has seen it's GNT#. in
cycle 3 your device (agent B) sees it's GNT# asserted. IRDY# is not
yet asserted and the registered FRAME# is still in inactive state
as well, so your device asserts FRAME# in order to start a transaction
and this way interferes with the transction of agent A.
            __    __    __    __    __
CLK       _| 1|__| 2|__| 3|__| 4|__| 5|_
                   ___________________
GNT#(A)   ________|
          ________             _______
GNT#(B)           |___________|
          ________       _____________
FRAME#(A)         |_____|_____________
          ______________
IRDY#(A)                |_____________
          ______________       _______
FRAME#(B)               |_____|_______
          ____________________
IRDY#(B)                      |_______

i hope my example is clear enough in order to reveal the potential
functional problem. being a PCI core designer on my own i don't
think you might be able to reduce the fanout on PCI bus signals
significantly by using the registered ones instead at such specific
points.

cheers!

  olaf
--
Olaf Reichenbaecher
Senior Design Engineer
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