If you are building a PCI bridge
chip, you have to be very careful. There are many PCI devices count on the delay
read timeout especially those have multiple functions. For example, the device
has 2 functions. Function 1 asks for a memory read. Before the data is returned,
function 2 generates a long memory burst write command. If the device decides that
the burst write command has a higher priority, then the device will try to
finish the long burst write command before it retry the read command. In case
the bridge chip gets the data between those 2 commands appear on the bus, it
will become a Delayed Read timeout situation. Because the bridge may try to meet
the PCI bus ordering requirements but the device wants to complete the burst
write command first. The device may or may not retry the memory read command
again. Even it eventually comes back and to retry the memory read command but
who knows when. Don’t count on the PCI device. Follow the PCI spec.
James.
-----Original
Message-----
From: Tony Clark
[mailto:Tony.Clark@EFI.COM]
Sent: Friday, January 12, 2001
6:59 AM
To: pci-sig@znyx.com
Subject: RE: Delayed Read Timeout
They test for this in the PCI compliance
workshop. I know because one of my boards failed the test when the
program was aborted with a ^c. Yet, I had never had a problem in any
Intel based system.
When the software was aborted, it would
disable the DMA controller while a retry was active and the pending retry would
never happen. I had to change the design so that the hardware would wait
until retry was complete before stopping.
I would suspect that other boards could
have similar problems. Many board designs never make it to a compliance
workshop and those that do may not have caught it during the brief test.
I would not have caught it if I had let the test complete, it just happened to
be running fine and time was running out, so I hit ^c.
Tony Clark
> -----Original Message-----
> From: duncan [mailto:duncan@mediaone.net]
> Sent: Thursday, January 11, 2001 6:36 PM
> To: pci-sig@znyx.com
> Subject: Delayed Read Timeout
>
>
>
> At one point DCelayed Read Timeout was explained as the
> answer to devices that issue speculative reads but never
> come back again for the data. Are there any PCI devices
> that actually do this?
>
> /SHD
>