[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: Problems with i21154 bridge

Let me describe briefly my problem and hope there's somebody out there
who can give me some hints:
Situation: Custom design with two i21154 PCI bridges (33-MHz version) in
the primary bus. Two PCI FPGAs (Lucent OR3LP26B) under each bridge. No PCI
Host in the primary bus yet, but a a PCI analyzer (Catalyst) is used for
bus scan instead.
Conditions (i21154 pins): P_M66ENA, S_M66ENA, CONFIG66, BPCCE, MSK_IN,
S_CFGN tied low. GPIOs pulled high. TRST (JTAG) tied low. Primary PCI
reset exceeds data sheet requirements. 15-MHz clock. Signaling enviroment
is 3.3V.
Problem: PCI bridges are not found during primary PCI bus scan. PCI
bridges do not generate clock on its secundary bus outputs ('1' in all
clock outputs) and secondary buses' reset is hold low by the bridges
Several PCI cards plugged in a test slot in the primary bus are found
during bus scan and R/W configuration operations to its registers are
carried out successfully.
Thank you for your time and for your help,
Jose Toledo
European Organization for Nuclear Research - CERN
Geneve, 23
CH-1211 (Switzerland)
EP division -- Electronic Design group (ED)
FAX: +41 22 767 9355
TEL: +41 22 767 8596