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RE: Problems with i21154 bridge
The Intel errata that Neal mentioned can be found at ...
Errata-6 appears to be a match, but it is reportedly much harder
Make sure that P_CLK is running well since it is the reference
for the clock outputs.
Make sure that SVIO is 3.3V to support your signaling
Monterey Design Center
Motorola Computer Group
From: Jose Franciso Toledo Alarcon [mailto:Jose.Toledo@cern.ch]
Sent: Monday, January 15, 2001 12:54 PM
Subject: Re: Problems with i21154 bridge
PCI bridges do not generate clock on its secundary bus outputs
('1' in all clock outputs) and secondary buses' reset is hold
low by the bridges permanently.