Problems with i21154 bridge (II)

[Jose Franciso Toledo Alarcon <Jose.Toledo@cern.ch>]

Hello,

A few days ago, I sent an email describing a problem with this PCI bridge.
I got several answers (thanks a lot!) and all of them pointed to a bug in
this chip (errata 6 in the specification update, dec.2000).

I've tried the two proposed workarounds...with no success so far.

According to Intel's description of the bug, secondary clock outputs
(s_clk_o<9..0>) should be driven low by the chip. What I observe is that
these outputs follow the 3.3V ramp and then remain high. Not low...
(yes, I checked there're not shorts to te power line :)

Intel also says that the bug manifests occasionally. In my case, it
manifests always. And I have two bridges on the board, behaving in the
same way. Doesn't look like bad soldering or anything like that, then.

Has anyone experienced the same discrepancies?.

Thanks a lot for your valuable help,

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Jose Toledo
European Organization for Nuclear Research - CERN
Geneve, 23
CH-1211 (Switzerland)

EP division -- Electronic Design group (ED)
FAX: +41 22 767 9355
TEL: +41 22 767 8596
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