FW: Problems with i21154 bridge (II)

[Jim Sather <jsather@sbs.com>]

Jose,

I've had some power up issues with 21154 but never failed to get a secondary
clock at power up once my MSKIN circuitry was working. You did not
specifically mention your clock connections other than MSKIN tied low. I
have worked with MSKIN low before, and that works. That will turn on all
your secondary clocks. Also, I have SCLK tied to one of the secondary clocks
through a 33 ohm resistor (and match that trace length to the other
secondary clock traces). Unused GPIO pulled up through resistors. All unused
SREQ lines pulled high ... you wouldn't want those floating. All errata
aside, I find once you get you basic connections, you get secondary clocks.

-----Original Message-----
From: Jose Franciso Toledo Alarcon [mailto:Jose.Toledo@cern.ch] 
Sent: Thursday, January 18, 2001 1:20 AM
To: pci-sig@znyx.com
Subject: Problems with i21154 bridge (II)


Hello,

A few days ago, I sent an email describing a problem with this PCI bridge.
I got several answers (thanks a lot!) and all of them pointed to a bug in
this chip (errata 6 in the specification update, dec.2000).

I've tried the two proposed workarounds...with no success so far.

According to Intel's description of the bug, secondary clock outputs
(s_clk_o<9..0>) should be driven low by the chip. What I observe is that
these outputs follow the 3.3V ramp and then remain high. Not low...
(yes, I checked there're not shorts to te power line :)

Intel also says that the bug manifests occasionally. In my case, it
manifests always. And I have two bridges on the board, behaving in the
same way. Doesn't look like bad soldering or anything like that, then.

Has anyone experienced the same discrepancies?.

Thanks a lot for your valuable help,

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Jose Toledo
European Organization for Nuclear Research - CERN
Geneve, 23
CH-1211 (Switzerland)

EP division -- Electronic Design group (ED)
FAX: +41 22 767 9355
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