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Re: Fw: a VHDL puzzle
Hi Neal,
Case statements don't solve the problem either:
for example you have 3 conditions:
OutBus <= a*ABus + b*BBus + c*CBus;
If a case statement is used, the following equation is expected to be
generated:
OutBus <= (a*!b*!c)*ABus + (!a*b*!c)*BBus + (!a*!b*c)*CBus;
And you have to experience a very laborious efforts to do that without any
implementation benefits.
Weng
----- Original Message -----
From: Neal Palmer <neal@dinigroup.com>
To: Weng Tianxiang <wtx@umem.com>
Sent: Tuesday, January 23, 2001 12:10 PM
Subject: Re: Fw: a VHDL puzzle
>
> How about a case statement?
>
> On Tue, 23 Jan 2001, Weng Tianxiang wrote:
>
> > Hi,
> > This topics is about a VHDL puzzle stemming from my designing process
for a PCI core.
> >
> > What does VHDL stand for? Virtual Hardware Design Language!?
> >
> > All hardware designs, no matter how complex they are, can be boiled down
to "OR" and "AND" operations.
> >
> > OutBus <= a*ABus + b*BBus + c*CBus + !(a+b+c)*OutBus;
> >
> > >From 80s' PAL to GAL to 90s' FPGA devices, all hardware structures make
the above equation implementation as fast as possible.
> >
> > Now I met a problem with PCI core design using VHDL: I found that VHDL
language definition lacks an inherent statement structure to implement the
above most important and basic equation.
> >
> > 1. The following is one example on how to write it:
> > ...
> > if(clk'event and clk = '1') then
> > if(a = '1') then
> > OutBus <= ABus;
> > elsif(b = '1') then
> > OutBus <= BBus;
> > elsif(c = '1') then
> > OutBus <= CBus;
> > end if;
> > end if;
> > ...
> >
> > After compiling and having a close look at the output equations, I found
what is generated is not what I wanted as above simple equation:
> >
> > OutBus(x) <= a*Abus(x) + !a*(b*BBus(x)) + !a*!b*(c*CBus(x)) +
not(a+b+c)*(OutBus(x));
> >
> > You can imagine it is not a surprise that an output bus for PCI core has
more than 20 data sources.
> >
> > While using if-elsif statement structures, designer had assumed to a
VHDL compiler that all conditions mentioned in the if or elsif statements
are MUTUALLY RELATED, EVEN THOUGH THEY MAY BE ACTUALLY MUTUALLY EXCLUSIVE! I
check my program and found in all state machines, conditions in if-elsif
statements are mutually related, but for most of data path, input or output
buses, conditions enabling data transfer are most MUTUALLY EXCLUSIVE.
> >
> > 2. Some may say you can device a function to deal with above equation:
> > BoolAndBus(a, b);
> > The following excerpt from my design shows you how difficult the
situation would become:
> > elsif(CLK66M'event and CLK66M = '1') then
> > if(TDMALowAD_R0ToLowData) then
> > case TDMAPtr(6 downto 3) is
> > when DMA_BATTERY_MAGIC => -- 0x00
> > ...
> > when DMA_EDC_LED => -- 0x08
> > if(nC_be_R0(0) = '0') then
> > ...
> > end if;
> >
> > when DMA_ERROR_DATA1 => -- 0x10
> > ...
> > elsif(MDMALowAD_R0ToLowData) then
> > case MDMAPtr(6 downto 3) is
> > when DMA_PCI_ADDRESS => -- 0x40: PCI address
> > if(nC_be_R0(0) = '0') then
> > ...
> > if(nC_be_R0(1) = '0') then
> > ...
> > elsif(...)
> >
> > end if;
> >
> > >From above example, you may see
> > 1. Target and Master are never doing same things at the same time. But
VHDL itself doesn't provide users with means to effectively express the
above situations.
> > In VHDL above implementation, I posed extra limitation on Target/Master
behavior that I don't want it.
> >
> > 2. BoolAndBus(a, b) function can work here, but you may know PCI bus is
64-bit width, I have to divide them into 8 Bytes and call 8 functions with
slightly different conditions. It totally destroy VHDL high language's
simplicity advantage!
> >
> > Now I need your help:
> >
> > 1. What is the best way to write the above equations in VHDL as simple
and as effective as ABEL or AHDL language?
> >
> > 2. I have a suggestions on VHDL language itself:
> > Why can't we add a new statement structure like the following for
sequence actions:
> > if(a = '1') then
> > OutBus <= ABus;
> > orif(b = '1') then <------ "orif" a
new key word is introduced here
> >
> > OutBus <= BBus;
> > orif(c = '1') then <------ "orif" a
new key word is introduced here
> >
> > OutBus <= CBus;
> > orif(not(a = '1' or b = '1' or c = '1')) then <------ "orif" a
new key word is introduced here
> >
> > OutBus <= OutBus;
> > end if;
> >
> > and similarly to add statement structures for global actions.
> > OutBus <= ABus when a = '1' elseor <------ "elseor" a new
key word is introduced here
> > BBus when b = '1' elseor <------ "elseor" a
new key word is introduced here
> > CBus when c = '1' elseor <------ "elseor" a
new key word is introduced here
> > OutBus;
> >
> > After compilation, it will generate equations like this:
> > OutBus <= a*ABus + b*BBus + c*CBus + not(a + b + c)*OutBus;
> >
> > 3. The following if-orif statement structure is what I really want from
VHDL:
> > elsif(CLK66M'event and CLK66M = '1') then
> > if(TDMALowAD_R0ToLowData) then
> > case TDMAPtr(6 downto 3) is
> > when DMA_BATTERY_MAGIC => -- 0x00
> > ...
> > when DMA_EDC_LED => -- 0x08
> > if(nC_be_R0(0) = '0') then
> > ...
> > end if;
> >
> > when DMA_ERROR_DATA1 => -- 0x10
> > ...
> > orif(MDMALowAD_R0ToLowData) then <------ "orif" a new key word
is introduced here
> > case MDMAPtr(6 downto 3) is
> > when DMA_PCI_ADDRESS => -- 0x40: PCI address
> > if(nC_be_R0(0) = '0') then
> > ...
> > if(nC_be_R0(1) = '0') then
> > ...
> > orif(...) <------
"orif" a new key word is introduced here
> >
> >
> > end if;
> >
> > IT IS VERY NATURAL TO ME THAT vhdl SHOULD INCLUDE A STATEMENT STRUCTURE
TO GENERATE THE BASIC LOGIC EQUATIONS WITH MUTUALLY EXCLUSIVE CONDITIONS FOR
HARDWARE DESIGN: OR and AND EQUATIONS WITHOUT ANY HUSSLE.
> >
> > 3. If anyone is fimilar with VHDL organization, could you please
transfer my suggestions to them.
> >
> > Thank you.
> >
> > Weng Tianxiang
> > Micro Memory Inc.
> > 9540 Vassar Av.
> > Chatsworth, CA 91311
> > Phone: 818-998-0070, Fax: 818-998-4459
> >
> >
>
> -- Neal Palmer
>
> The Dini Group
> 1010 Pearl St #6
> La Jolla, CA 92037
> (858) 454-3419 x16
> (858) 454-1728 (Fax)
>
>
>