[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: Fw: a VHDL puzzle




Be careful of doing A + B + C !== 1'b1 because the verilog spec defines it
to generate a 1 bit output.  And simulators and synthesis tools might
treat it differently (when they don't exactly follow the spec)!


On Tue, 23 Jan 2001, Kevin Normoyle wrote:

> [snipped much detail about getting priority decoders in 
> rtl, rather than muxes]
> 
> > IT IS VERY NATURAL TO ME THAT vhdl SHOULD INCLUDE A STATEMENT STRUCTURE 
> > TO GENERATE THE BASIC LOGIC EQUATIONS WITH MUTUALLY EXCLUSIVE CONDITIONS 
> > FOR HARDWARE DESIGN: OR and AND EQUATIONS WITHOUT ANY HUSSLE.
> 
> 
> Yup. It's a big problem. Same thing with verilog.
> Lots of gates generated where they're not needed.
> 
> Here's my favorite way to "do a reasonable thing" in verilog.
> 
> Assume you have mutually exclusive selects (one-bit) A,B,C,D
> and they control 32 bit data onto a 32-bit output.
> 
> Note, this will propagate X's correctly, unlike some 
> other verilog behavioral code constructs.
> 
> assign data[31:0] = 
> 	(A==1'b1) ? (data_in_A[31:0] : 32'b0) |
> 	(B==1'b1) ? (data_in_B[31:0] : 32'b0) |
> 	(C==1'b1) ? (data_in_C[31:0] : 32'b0) |
> 	(D==1'b1) ? (data_in_D[31:0] : 32'b0) ;
> 
> The control equations can be arbitrarily complex, if you don't have
> single bit contorl signals.
> 
> Clumsy. But I share you pain at the rtl languages actually causing
> problems, rather than solving them. 
> 
> It usually pays to also have a monitor to check that the controls really are 
> exclusive.
> 
> i.e.
> 
> if (A + B + C + D !==1'b1) begin ....error message.... end
> 
> This enforces one-hot-ness. Sometimes you don't need that...so you can do
>  
> if ((A + B + C + D !==1'b1) & (A + B + C + D != 1'b0)) begin ....error message.... end
> 
> To just check "not more than one selected".
> 
> Remember, we're not just talking about "synthesizing" with knownledge
> of mutually exclusivity, but we want the rtl to simulate logically like
> the final gate result. That's why use of case statements is rough in rtl,
> (first case is executed only).
> And nested if/else produces a priority encoder.
> 
> A slightly different definition for "case" would have done the trick.
> But you really want both cases. :)
> 
> -kevin
> 

-- Neal Palmer

The Dini Group
1010 Pearl St #6
La Jolla, CA 92037
(858) 454-3419 x16
(858) 454-1728 (Fax)