[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

RE: PCI-X I/O pads

> -----Original Message-----
> From: Ingraham, Andrew [mailto:Andrew.Ingraham@compaq.com]
> Sent: Friday, January 26, 2001 14:37
> To: 'Vikas M'
> Cc: pci-sig@znyx.com
> Subject: RE: PCI-X I/O pads
> > I would appreciate if somebody can provide some idea on how
> this timing of
> > 3.8ns can be achieved if the PCI-X I/O pad delay itself is
> around 2.5ns ?
> If the output buffer delay is sufficiently constrained (doesn't
> have a huge
> range between min. and max. delays), then a PLL in the clock path might
> help.  You can use the PLL to advance the internal clock.

Beware that this might conflict with the requirement for PCI-X devices to be
able to operate in PCI 33 mode. The PCI 33 mode allows the clock to go down
to 0 Hz, and no PLL can track this. Thus the PLL must be bypassed in the PCI
33 mode. PCI 33 will anyhow not need the PLL to meet the timing

You might also have to set the PLL configuration differently for PCI-X
133/66 and PCI 66 modes to cover the respective frequency ranges.

- Olaf