I suppose the clock interstion delay of 0.5 nsec is pretty much good
You cannot get less than that.
But what you should look for is a output flop in the IO cell itself.
Thats the key to meeting the PCI-X timings !!
So you io flop should have one input flop, one output flop and tri-state buffer as well as input buffer.
You can check NEC 0.18 lib on their web for PCI-X IO cell
I suppose they have these type of io cells avaiable.
Ajit Madhekar wrote:
> The delay in this path is
> clock-to-Q of flop ( 0.6),> Buffer delay (0.6ns),> the PCI-X I/O pad delay ( 2.3ns ) Is it a worst case timing ? What is a typical delay of above path ? Which Library you are using ? > and a clock insertion delay (0.5ns ). Is it insertion delay + skew ? If so, then thats pretty much good delay. Regards,Ajit