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Re: target single data

Hi,
1. Assert your nDEVSEL when transaction address hits your Target address;
2. When your Target is ready, assert nTRDY and nSTOP at the same time; 1 and 2 can be combined if you are sure your Target is ready to do it;
3. When single data is accessed, deassert nTRDY and keep nSTOP asserted until last transaction cycle.
4. You don't have to do anything else.
 
Weng Tianxiang
Micro Memory Inc.
9540 Vassar Av.
Chatsworth, CA 91311
Phone: 818-998-0070, Fax: 818-998-4459
 
----- Original Message -----
From: Daniel DeConinck
To: pci-sig@znyx.com
Sent: Saturday, October 14, 2000 11:22 AM
Subject: target single data

Hi,
 
I am designing a target that does not autoincrement addresses.
 
I want to minimize the time between master writes. The master will be wanting to provide data on successive clocks yet I can only take one data phase per transaction.
 
So the question is how should the target handle the single data phase to acheive minimum delay before the next master initiated write ?
 
Currently the target sends #TRDY & #DEVSEL inactive after reading the data and then the target just waits for the next master write. How does the master decide to give up the attempt to write consecutive data based on how my target currently handles the transaction? What would the proper way be to inform the master that the target is only accepting this one data phase.
 
How fast would the master turn around and start the next write ?
 
Sincerely
Daniel DeConinck
High Res Technologies, Inc.