PCI Device Status Register

[Manfred Kuhland <man@atlantek.com.au>]

Hi,
Can anyone shed some light on the functionality of the "Signalled Target
Abort",
"Received Target Abort" and "Received Master Abort" bits in the Device
Status
Register of the PCI Configuration Space?

If any one of these abnormal cycle termination's occur the Target or
Master (whatever
the case may be) must set the relevant bit in the Device Status
Register. So far that's
pretty easy to understand. But how are these bits used from there on?

Does the OS or BIOS or Device Driver supposed to read the register and
do something
with it? How does any of these routines know that the register bits have
been set?
Polling the Device Status Register every now and then? Or generate an
interrupt to the
Device Driver?

A Target or Master-Abort is obviously a very serious event which should
be reported
(and acted on) as soon as possible. Any feedback would be appreciated.

Thanks for your help.

Manfred Kuhland
Director - Electronic Engineering
Atlantek Microsystems Pty Ltd
Innovation House, Technology Park,
Mawson Lakes, SA, 5095, AUSTRALIA

Tel:         +61-8-8260-8990
Fax:        +61-8-8349-4286
E-mail:    man@atlantek.com.au
Internet:  http://www.atlantek.com.au