RE: Programmable BARS

[Lame Brooks-G14738 <brooks.lame@motorola.com>]

Yes, you're missing something; there must be something to uniquely identify
each different application implementation of your silicon.  Typically, this
is done with a combination of the Vendor ID, Device ID, Subsystem Vendor ID,
Subsystem ID, and Revision numbers.  The OS code that does driver
association trys to find the driver that identifies itself for use with a
device matching those numbers and it's assumed that an implementation with
such a particular ID set uses the particular BARs in a known way.
-- BrooksL

> -----Original Message-----
> From: James Murray [mailto:jmurray@triscend.com]
> Sent: Wednesday, 14 March, 2001 11:38
> To: PCI SIG
> Subject: Programmable BARS
> 
> 
> Hello
> 
> I was thinking of using 6 memory BARS in an ASIC, and having the
> capability to "map" each one these BARS to one of 8 possible 
> application
> memory targets.  The number of BARS implemented and the memory area to
> which the BARS are assigned will depend on the particular 
> application of
> the ASIC.
> 
> My question is: If I implement such a scheme, how does an external bus
> master know which BARS correspond to what areas in my 
> application? Since
> the BARS are not fixed relative to one another, I cannot see how this
> will work, if at all?
> 
> Is my scheme not valid or am I missing something?
> 
> Any help would be greatly appreciated.
> 
> James Murray
>