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RE: Programmable BARS
Say you have 32 meg ram, and 4K of control registers -
if you don't use 2 BARS, the board has to request 32 meg PCI space.
If you use 2 bars, then it can use up 16 meg, plus 4K.
Why should you care? Some current popular commercial OS's have a maximum
limit of 192 meg (I forget the number precisely), so if you use up
too much space on one device, you might not be able to fill a Compact PCI
Rack with boards..
From: Henry Gong [mailto:firstname.lastname@example.org]
Sent: Wednesday, March 14, 2001 2:14 PM
To: James Murray
Cc: PCI SIG; email@example.com
Subject: Re: Programmable BARS
Can you tell me the benift to separate memory into a few sections? I never
For your case, your driver must know which application uses how much memory
which is defined in the BARs. So your driver should know which BAR is for
which application. Except your own driver, who else knows how you use these
memories? So called "external bus master" must be operated by your driver
or by an application software which will access your driver.
If you map these memories in one BAR, the whole allocated memory is still
fully under the control of your driver. This has been always the way how we
use the BAR in my previous PCI projects. And this is why I do not
understand why 6 BARs are available in configuration space. Can anybody
lighten me please.
North Ryde Australia
James Murray wrote:
> I was thinking of using 6 memory BARS in an ASIC, and having the
> capability to "map" each one these BARS to one of 8 possible application
> memory targets. The number of BARS implemented and the memory area to
> which the BARS are assigned will depend on the particular application of
> the ASIC.
> My question is: If I implement such a scheme, how does an external bus
> master know which BARS correspond to what areas in my application? Since
> the BARS are not fixed relative to one another, I cannot see how this
> will work, if at all?
> Is my scheme not valid or am I missing something?
> Any help would be greatly appreciated.
> James Murray