RE: PCI under reset

[Lame Brooks-G14738 <brooks.lame@motorola.com>]

As long as you meet the setup and hold timing requirements for Reset and
don't change things during that time, you're fine; it seems you may do
almost what ever you want before then.  -- BrooksL

> -----Original Message-----
> From: Michael Yin [mailto:Michaely@teralogic-inc.com]
> Sent: Friday, 16 March, 2001 15:23
> To: 'pci-sig@znyx.com'
> Subject: PCI under reset
> 
> 
>    I have a question on the PCI spec.
> The spec says that "To prevent AD, C/BE#, and PAR signals 
> from floating
> during reset, the central resource may drive these line 
> during reset (bus
> parking) but only to a logic low level; they may not be driven high."
>    What is the reason? 
>    What if these signals are toggled for a few micro seconds 
> while the reset
> is active?
> 
> Thanks in advance,
> Michael
> 
>