RE: PCI under reset

["Olaf Birkeland" <olaf.birkeland@fast.no>]

> -----Original Message-----
> From: Michael Yin [mailto:Michaely@teralogic-inc.com]
> Sent: Saturday, March 17, 2001 12:23 AM
> To: 'pci-sig@znyx.com'
> Subject: PCI under reset
>
>    I have a question on the PCI spec.
> The spec says that "To prevent AD, C/BE#, and PAR signals from floating
> during reset, the central resource may drive these line during reset (bus
> parking) but only to a logic low level; they may not be driven high."
>    What is the reason?
>    What if these signals are toggled for a few micro seconds
> while the reset
> is active?
>

Floating signals are generally undesirable in any system, as an input pin
connected to a floating signal might end up in the transition region with
both the n- and p-channel transistors of the input buffer conducting. This
will cause excessive current consumption, potentially also damaging the
component.

Most PCI implementations tri-state these pins during reset, and rely on an
external pull-up resistor to bring the bus to a defined level.

Regards,
- Olaf