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Initialization Phase versus Run Time Phase
I have an ASIC which could potentially require a relatively long time (3
seconds) to initialize itself before being ready for access from an
external bus master.
After PCI RST is deaseerted, my device will assert an automatic "Retry"
if accessed before my PCI config registers have been configured
correctly (loaded from EEPROM for example).
My first question is: Can I assert this "retry" for up to 1 second,
(2^25 PCI clocks) without any side effects?
After the 1 second period elapses, the system is now in "Run-time"
phase, however, my device is still not ready to be accessed, since it
has other initialization tasks that take a long time to complete. If I
am now accessed by a PCI bus Master, I could Retry it again, but the
spec says that for Mmeory Write, I need to accept at least 1 data phase
within 10usecs after the first retry. (Section 3.5.3)
How do I "hold-off" external bus master acccess to my device until I am
ready to accept them? Is it reasonable for me to implement a "Ready"
register that can be accessed after initialization, that will indicate
that I am not ready to external bus masters? If not, any suggestions?