RE: 66MHz PCI timing

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> I noticed that the timing parameters for 66MHz PCI assumes an ouput load
> of 10pF whereas the 33MHz PCI timing assumes 50pF. Is this basically
> saying that with 66MHz PCI you can ONLY have 1 other device on the bus,
> since a typical device has an input C of 10pF. Also, I assume an edge
> connector would be out of the question given the extra C associated with
> it.
 
Careful.  The test load for 66 MHz PCI (and 33 MHz when designed for 3.3 V
signaling) is a 25 ohm resistor.  The 10 pF capacitor is there because of
the inevitable input capacitance of test equipment.

This test load is designed to test the ability of the output buffer to drive
into the middle of a transmission line, during the first couple of
nanoseconds after switching, before the signal reflects off the ends of the
bus and returns to the driver.

The higher switching speeds involved in modern circuits, requires a mindset
change.  You can't treat real loads and traces as lumped capacitors anymore.
When the driven waveform switches significantly before the leading edge
reaches all devices on the bus, you really need to treat the load as a
complex circuit made up of transmission lines and such.  The old 50 pF test
load that dates back to the 1960's, is inadequate for modeling that
situation.

Plug-in cards are allowed and used at 66 MHz.  The connector itself isn't
the problem; it's the trace "stubs" on the card.  Practically speaking, more
than one load at 66 MHz PCI, on a plug-in card with an edge connector, may
be difficult, but is not necessarily impossible.  It does get better if
everything is planar (no plug-in cards) because the trace lengths can be
shorter and you can avoid "stubs."

Andy