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I am working on a group developing a PCI board for data acquisition.
Since our priority is getting it running, busmastering capabilities for
such things as DMA to the host memory are not on the front line of
Now, since I'm the guy behing the device driver, I have done some
benchmarking with a simple device driver (in Linux, of course) using a
standar PCI VGA adapter.
This "driver" just uses the memcpy() transfer some data between the main
memory and the board's framebuffer.
I have tried three different processor/chipset combinations and the
results I get, are:
(results after BIOS and MTRR parameters tweaking)
Intel 440FX (PII@233) 7.03
Intel 440BX (2*PII@400) 8.62 102.4
VIA KT133 (Athlon@900) 7.46 119.6
Now this points to a pattern in which the north bridge seems unable to
read with a reasonable speed from the board. I know writing is always
easier than reading (from the specs a single data phase read is slower
than a single data phase write (4 clock cycles vs. 3)).
The north bridge behaviour is inadmissible even if we assume that all
the reads are single data phase reads (4 clock cycles), with even medium
devsel (1 more clock cycle lost) and a wait-state from the VGA board
(another clock sycle lost), because this would give a total of 6 clock
cycles, or 22Mb/s total bandwidth.
So my questions are:
- Since it looks that north bridges have always been like this, has
anyone found one that is not?
- Is it admissible (logical) that the north bridge is like this?
- Since I have only talked about commodity PC's, could there be
something on the industrial market that does not suffer from this
Thanks in advance for all comments,
org:CERN - Centre Europeen de Recherche Nucleaire;Experimental Physics Division - NA60 Experiment