Mixed byte enables during PCI burst transaction

[Tim Fairfield <fairfield@canada.com>]

When performing burst writes in PCI , is it legal to change the byte lanes during the burst? I cannot find anything in the spec which either confirms or denies this.

One PCI cycle could look like this.

[   16   ]
[        32        ]
[        32        ]
[        32        ]
               [ 8 ]

Any aligned or non-aligned byte transfer is possible. The bytes would always be contiguously addressed.

Any help would be appreciated,
Thanks
-Tim

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