Re: Mixed byte enables during PCI burst transaction

[lecos@samsung.co.kr]

Yes. It is legal. Your byte enables combinations are,
generally speaking, somewhat simple. PCI target devices
must accept more complicate burst transfer as follwing.

CLK=1	ADDR=..00h : BE#=1100
CLK=2	ADDR=..04h : BE#=1001 (not aligned)
CLK=3	ADDR=..08h : BE#=0110 (split)
CLK=4	ADDR=..0Ch : BE#=1111 (null)
CLK=5	ADDR=..10h : BE#=0000

Most master device doesn't use above not-aligned, split, 
and null byte enables. But according to Spec. all byte
enable combinations must be accepted.

I couldn't find these descriptions examples in the Spec.
Related descriptions are..
-PCI Local Bus Spec. 2.2  p.28    ($3.2.2.1)
-PCI Local Bus Spec. 2.2 pp.28-30 ($3.2.2.2)


> When performing burst writes in PCI , is it legal to change the byte lanes during the burst? 
> I cannot find anything in the spec which either confirms or denies this.
> 
> One PCI cycle could look like this.
> 
> [   16   ]
> [        32        ]
> [        32        ]
> [        32        ]
>                [ 8 ]
> 
> Any aligned or non-aligned byte transfer is possible. The bytes would always be contiguously addressed.
> 
> Any help would be appreciated,
> Thanks
> -Tim
> 
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 +++  LECOS (Lee, Cheon-Su), +82-31-209-2826, lecos@samsung.co.kr
 +++  Engineer / Network / C&C SOC Products / Samsung Semiconductors
 +++  San#24, Nongseo-Ri, Kiheung-Eup, Yongin-City, Kyunggi-Do, Korea