Re: Why cannot Target change its mind

[Joseph W Schulingkamp <jschulingkamp@agere.com>]

To answer #2 first - refer to PCI 2.2 p. 51, item #4:

"4.  Once a master has asserted IRDY#, it cannot change IRDY# or FRAME# until
the
        current data phase completes."

Once a device commits to a  data transfer, it must complete it.
When the target asserts TRDY# during a read, it should also be driving and
maintaining data.  If IRDY# is high, the master is inserting wait states - one
reason it may be doing this is to give itself more time to process the data (a
parity
check on a slow master, for instance).

In other words, the master doesn't only insert wait states because it not ready
to
accept the data, but also because it needs an extra time to handle the data.

The same thing can happen for a write cycle - the master must maintain
data once IRDY# is asserted, even if the target inserts wait states by
deasserting TRDY#.


            Joe



Weng wrote:

> Hi,PCI 2.2 p.53: Once a target has asserted TRDY# or STOP#, it cannot change
> DEVSEL#, TRDY#, or STOP# until the current data phase completes. I have two
> questions about the above definition. The reason that DEVSEL# and STOP# cannot
> be changed is clear, I don't see any merit why TRDY# cannot be changed if
> Target found Master is asserting wait cycles and it wants to change mind
> too. 1. On what senerio the changing TRDY# signal will have permanent damage
> to any transactions? When I have been designing Master module, I don't see any
> difference in design whether or not PCI-Target is changing its mind. The only
> logic that go into my design is IRDY# = '0' and (TRDY# = '0' or STOP# = '0'),
> that means only when both Master and Target agree with a transaction, the deal
> is made, otherwise wait until the above conditions happen. 2. While not
> allowing Target to change its mind, why there is no symmetrical limit on
> Master side, that is, on IRDY#? My opinion is: (a relaxed condition that is
> good enough to match original definition)Once a target has asserted DEVSEL# or
> STOP#, it must be asserted until a transaction is finished. Data is transfered
> only on conditions that IRDY# = '0' and TRDY# = '0'. Target can change TRDY#
> state if no data is transfered. Weng Tianxiang wtx@umem.com
> wengtianxiang@yahoo.com Micro Memory Inc.
> 9540 Vassar Avenue
> Chartsworth, CA 91311
> Tel: 818-998-0070
> Fax: 818-998-4459
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