PCI ARBITRATION & INTERRUPTS

["SUSHANT S RANADE" <ssr@myw.ltindia.com>]

Hi all, 

I am designing a single function (with support to dma master and single read/wriet target mode for real-time data scanning) I have some doubt regarding PCI Arbitration and interrupt handelling. 

1.
I want to design a card which is transferring image data to PC RAM through PCI in master mode . In my system there is only one PCI Bus having some other PCI base devices also. And I want to have the highest priority for my add-on card to transfer the real-time data. 
So can anybody telll me how to set the priorities for the device in the PCI Arbiter.

2.
according to pci2.2 specs one function can use one interrupt at the max. wich can be  multiplexed for different operations according to PLX9054 documentation section 2(configuration modified by local side, dma operations, doorbell register, mailbox register, etc.) which are ORed to form one INTx line for say irq11. also according to pci 2.2 specs for interrupt acknowledge cycle is implicitly driven for interrupt controller, then how come the interrupt controller come to know the vector address if for which operation of the function?
 what i am thinking is the interrupting device should give the offset of the vector address for that operation identification, but then for positive address decoding, there is no valid address for the interrupt acknowledge cycle, so how the device responds?

so should my device support to interrupt acknowledge cycles or not?

3.
I am having one more doubt. if my master is tring to lock any target which is on other bus (say PC RAM on host local bus) is it possible for resourse lock condition? if yes can i do the posted write to the locked target? how? does the bridge in between gets locked? or for posted it generates seperate lock cycle? 


 waiting for any solutions or the links / related information regarding it. 

With Kind Regards, 

RANADE SUSHANT

ADesign Engg.
EmSyS,L&T,
Mysore,INDIA
ssr@myw.ltindia.com