FW: PCI Configuration Registers accessed by 3rd device and not PCI Host

["Srividya Viswanathan" <srividya.viswanathan@idt.com>]

-----Original Message-----
From: Srividya Viswanathan [mailto:srividya.viswanathan@idt.com]
Sent: Monday, April 16, 2001 2:55 PM
To: Deepesh Tiwari
Cc: pci-sig@zynx.com
Subject: RE: PCI Configuration Registers accessed by 3rd device and not
PCI Host


What you say seems reasonable. But once that bit is cleared, do u still
allow the PCI Host to monitor and update the configuration registers? I am
guessing, that u would still allow the Host to clear the Status register
bits etc.

About the Dallas Semiconductor Design I was talking about, the local bus is
set in one of 2 modes by an external pin. There is no elaboration on how the
"IDSEL" is disabled. In the Config Mode, the Local CPU will set and monitor
the PCI Config registers. There is a blanket statement saying
"The Host on PCI bus cannot access the device". It is this part which sounds
strange to me.

Vidya

-----Original Message-----
From: Deepesh Tiwari [mailto:deepesh@us.ibm.com]
Sent: Monday, April 16, 2001 2:28 PM
To: Srividya Viswanathan
Subject: Re: PCI Configuration Registers accessed by 3rd device and not
PCI Host


Can you please elaborate When you say IDSEL is "disabed" .
We have a similar Design, but we have a bit in a register inside ourDesign.
When local CPU sets this bit for completing all the initializations, all
the config accesses from
the host are RETRY(retried), until the Local cpu initialization is complete
and it clears this bit.

See if that fits to your scenario
--Deepesh Tiwari

"Srividya Viswanathan" <srividya.viswanathan@idt.com> on 04/16/2001
02:28:40 PM

To:   <pci-sig@znyx.com>
cc:
Subject:  PCI Configuration Registers accessed by 3rd device and not PCI
      Host



Hello PCI Experts

I am looking at a Dallas Semiconductor design which has a local bus and a
PCI Bus. The local bus has 2 modes

1) Normal/ Bridge Mode
In this mode, the PCI Host initializes all device specific config.
registers
and PCI Config registers.
The PCI Host can access any  memory on the local bus (from the PCI bus - to
device - to local bus).
Application data transfer happens between the device and Host Memory
through
PCI bus.

2) Configuration Mode
In this mode, the local CPU initializes all device specific config
registers
AND PCI CONFIG. REGISTERS.
In this case, the IDSEL of PCI bus is disabled. The PCI Host cannot access
the device at all.
Application data is still transfered between the device and host memory
through PCI Bus.

My questions are regarding the Configuration Mode and the local CPU
accessing the PCI Config registers

1) Is accessing of PCI Config registers by a 3rd party a common practice?
2) Does it confirm to the PCI/PCI-X specification? Especially since IDSEL
is
"disabled".
3) What happens if the PCI Host does initiate a PCI Config. Cycle to the
device?

Any help will be appreciated.
Please reply directly to me

Regards
Vidya
--
Vidya Viswanathan
IDT Dallas Design Center,
Ph: 972-244-2141