Re: why Target cannot change its mind

[Joseph W Schulingkamp <jschulingkamp@agere.com>]

Richard Iachetta wrote:

> >I have to say that I have never backed out from my original view:
> >"when Either Master or Target is inserting wait cycles, NOT FOR LAST DATA
> >(FRAME# = '0'), the opposite partner can change its state (IRDY# or TRDY#)
> >without any harm if no accompanying STOP# change !!! That's all."
>
> Weng,
>
> Can you explain why a target would ever want to assert its TRDY# and then
> later change its mind before the data was transferred?  What benefit could
> be gained by having the bus support that?
>
> Rich Iachetta
> IBM Microelectronics Division -- Austin
> World Wide Field Design Center
> Phone: 512-838-6305   Tie Line: 678-6305

And why this would be a less complex or more efficient design?  At any level
(e.g.
chip, board or system)?