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Fw: Why cannot Target change its mind
----- Original Message -----
Sent: Friday, April 13, 2001 2:01 PM
Subject: Why cannot Target change its mind
Hi,
PCI 2.2 p.53: Once a target has asserted TRDY# or
STOP#, it cannot change DEVSEL#, TRDY#, or STOP# until the current data
phase completes.
I
have two questions about the above definition.
The reason that DEVSEL# and STOP# cannot be changed
is clear, I don't see any merit why TRDY# cannot be changed if Target found Master is asserting wait cycles and it wants
to change mind too.
1. On what senerio the
changing TRDY# signal will have permanent damage to any
transactions?
When I have been designing Master module, I
don't see any difference in design whether or not PCI-Target is changing
its mind. The only logic that go into my design is IRDY# = '0' and (TRDY# = '0'
or STOP# = '0'), that means only when both Master and Target agree with a
transaction, the deal is made, otherwise wait until the above conditions
happen.
2. While not allowing Target to change its mind,
why there is no symmetrical limit on Master side, that is, on
IRDY#?
My opinion is: (a relaxed condition that is good
enough to match original definition)
Once a target has asserted DEVSEL# or STOP#, it
must be asserted until a transaction is finished. Data is transfered only on
conditions that IRDY# = '0' and TRDY# = '0'. Target can change TRDY# state if no
data is transfered.
Weng Tianxiang
Micro Memory Inc.
9540 Vassar
Avenue
Chartsworth, CA 91311
Tel: 818-998-0070
Fax:
818-998-4459