Re: Purposeful Parity control

[Dimiter Popoff <tgi@bulnet.bg>]

>> Why was the parity control necessary for a chip-to-chip bus?
>
>For the same reason it's necessary in other reliable, high-speed data
>transfer mechanisms - it is very easy for single bit errors to sneak in, be
>they due to design margin, bad components, external influence, or whatever,
>and without some bandwidth-efficient, cost-effective detection method, a
>single bit error could easily run undetected for a while and worm its way
>into causing system instability.

Do you believe parity check could measurably compensate for
"design margin, bad components, external influence, or whatever" ?
The systems I have seen either work and make no errors so
parity control has nothing to do all the time
or make too many errors and parity control is useless.

Which chip-to-chip PCI based device do you know to recover
from parity error and continue?

What is the typical system behaviour today upon parity error?

Dimiter