[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

RE: Purposeful Parity control




	If some hardware deep within your bank's computer suffered a parity
error,
would you rather have it:

	- do nothing, the parity error gets written into the database,
corrupting
	data, eventually causing several problems costing serious time and
effort to
	sort out,
	Or,
	- crash immediately, identifying right now that there is a problem,
and
	exactly which board it came from?

Now I realize this is a contrived example, I would assume the bank uses
error correcting
hardware, but who knows?
Gord Wait


-----Original Message-----
From: Dimiter Popoff [mailto:tgi@bulnet.bg]
Sent: Tuesday, April 17, 2001 2:28 PM
To: pci-sig@znyx.com
Subject: Re: Purposeful Parity control



>> Why was the parity control necessary for a chip-to-chip bus?
>
>For the same reason it's necessary in other reliable, high-speed data
>transfer mechanisms - it is very easy for single bit errors to sneak in, be
>they due to design margin, bad components, external influence, or whatever,
>and without some bandwidth-efficient, cost-effective detection method, a
>single bit error could easily run undetected for a while and worm its way
>into causing system instability.

Do you believe parity check could measurably compensate for
"design margin, bad components, external influence, or whatever" ?
The systems I have seen either work and make no errors so
parity control has nothing to do all the time
or make too many errors and parity control is useless.

Which chip-to-chip PCI based device do you know to recover
from parity error and continue?

What is the typical system behaviour today upon parity error?

Dimiter