Re:Re:PCI ARBITRATION & INTERRUPTS

["SUSHANT S RANADE" <ssr@myw.ltindia.com>]

hi,

still i have some doubts.

1. so my device will not support the INTACK cycle, and my ISR should read some status register to find out which function/operation or their combination is interrupting. but for this reading, when host-pci bridge wants to drive the cycle, ans suppose currently the pci bus is granted to some other master(which is not controllable by host or s/w) who is bursting heavily to some other tatget. so to get the bus grant the host-pci bridge will need to wait for long time.
still can we consider the interrupt / its servising as asynchronous, meaning having ability to stop other operations and perform certain operatin? as it takes such time weaste to just know actually which operation is interrupting, or the servising interrupt also depends upon other devices. 

2. o.k. i got it. i can't lock any RAM on the host's local side. that means the device driver should lock the swaping of pages. so is it possible to get a physical address to which my IDMA on device to transfer data.
in my condition, i want to transfer 200 DWORDS(1 beam) as single IDMA operation and such 800 beams to form 1 image. so at the time of configuration can i fix the dma's destination address (physical) as it is realtime operation and is not in control of the device driver / host. so untill i turn off my application the destination address of dma should be fixed otherwise i have to get the same before each of my dma operation resulting in time weaste and unnecessary exrta cycle.

hope you got my problem, waiting for reply.

with kind regards.

RANADE SUSHANT
ADesign Engg.
EmSyS,L&T,
Mysore,INDIA

-------------------------------
                
  Mail Message  
From: Richard Walter <rwalter@brocade.com> 
To: SUSHANT S RANADE  
Subject: RE: PCI ARBITRATION & INTERRUPTS 
Attachments:  Mime.822  (Save As: Binary, Size=6277 bytes)  
Message: > 1. 
> I want to design a card which is transferring image data to PC RAM 
> through PCI in master mode . In my system there is only one PCI Bus 
> having some other PCI base devices also. And I want to have the highest 
> priority for my add-on card to transfer the real-time data. 
> So can anybody tell me how to set the priorities for the device in 
> the PCI Arbiter. 

Generally, you can't set priorities in the arbiter. The PCI arbiter is 
not specificed by the PCI spec, other than to say that it must be fair. 
The actual register level implementation for a specific arbiter can change 
from board to board. 

The proper way of trying to get more bandwidth for your device is to 
use the Min_Gnt & Max_Lat registers to tell the configurator that you 
have specific requirements. In the best case, the configurator will 
take this info into account when programming the latency timer registers 
in config space of all PCI devices, which hopefully results in your 
device getting the bandwidth it needs. 

If you want to experiment, you can change the latency timers of devices, 
setting yours high and everyone else's low. However, such a solution is 
frowned upon in the real world because you really shouldn't be changing 
other device's settings. 

In general, PCI does not guarantee bandwidth. 

> 2. 
> according to pci2.2 specs one function can use one interrupt at the 
> max. wich can be multiplexed for different operations according to 
> PLX9054 documentation section 2(configuration modified by local side, 
> dma operations, doorbell register, mailbox register, etc.) which are 
> ORed to form one INTx line for say irq11. also according to pci 2.2 
> specs for interrupt acknowledge cycle is implicitly driven for interrupt 
> controller, then how come the interrupt controller come to know the 
> vector address if for which operation of the function? 

The interrupt controller doesn't know which function is interrupting. 
The interrupt service routine software must check for this. 

PCI interrupts are sharable and their sharing is system dependent. 
This means that you, as a card vendor, have no control over what the 
interrupt mapping is. 

When the PCI configurator sets up the bus, it uses the INT_PIN register 
to determine if the function needs an interrupt assigned to it. The 
configurator will determine what your interrupt pin is connected to and 
will place the vector number into the INT_LINE register. This is the 
vector that the interrupt controller will return when responding to 
INTACK cycles. 

When your driver software loads, it reads the INT_LINE register, and 
installs itself on that vector. Note that many drivers may be installing 
themselves on this same vector. When an interrupt occurs, the interrupt 
controller will return this vector and the OS will begin to call the 
drivers, asking each to look at some device specific register to determine 
if it's device is the one that is currently interrupting. 

So, for your PLX implementation, if you use DMA, doorbell, and mailboxes, 
then you will write one interrupt service routine. When that routine is 
entered, your code should read some status registers in the PLX to determine 
if the DMA is interrupting, the doorbell is interrupting, the mailbox is 
interrupting (or some combination of these) and handle those conditions. 

> what i am thinking is the interrupting device should give the offset 
> of the vector address for that operation identification, but then for 
> positive address decoding, there is no valid address for the interrupt 
> acknowledge cycle, so how the device responds? 

> so should my device support to interrupt acknowledge cycles or not? 

No. Only interrupt controllers respond to interrupt acknowledge cycles. 
Your device should not. 

> 3. 
> I am having one more doubt. if my master is tring to lock any target 
> which is on other bus (say PC RAM on host local bus) is it possible 
> for resourse lock condition? if yes can i do the posted write to the 
> locked target? how? does the bridge in between gets locked? or for 
> posted it generates seperate lock cycle? 

You really don't want to use locked cycles. In fact, at some point 
(I don't remember if it was 2.1 or 2.2), general locking became prohibited 
by the spec and currently the only valid use of lock is when doing a 
read/modify/write cycle of a 4-byte word or less. In fact, I believe 
that most Intel host chipsets don't even have a lock# pin on them 
anymore... 

If you're just reading & writing memory, there is no need to lock it. 
Software must ensure that buffers stay put and there are OS calls to 
allocate memory and lock it down so that it is not moved or swapped. 

Also, be aware that most modern OS's operate software in virtual address 
space, while PCI is physical address space, so there is some amount of 
OS level mapping that must be done so that software can talk to the 
PCI devices and give the devices pointers to memory. 

> With Kind Regards, 

> RANADE SUSHANT 
> ADesign Engg. 
> EmSyS,L&T, 
> Mysore,INDIA 
> ssr@myw.ltindia.com 

-Richard Walter 
Senior Hardware Engineer 
rwalter@brocade.com 
Note: I speak for myself, not for Brocade.