RE: Purposeful Parity control

[Wen-King Su <wen-king@myri.com>]

>This has denegrated right down to me level...
>
>Parity was and remains useful to detect fatal, data corruption, so
>that corruption isn't silent, which is an even worse sin
>than non-detected corruption.

I want to point out that PCI spec does not require the ASICs to parity
check their internal datapaths, and I bet none do.  They contain bits
that can be flipped by cosmic ray, and they contain transistors with
gate oxide that can trap and retain cosmic ray induced electrons which
shift their threshold voltage over time.  But there is no thought of
doing parity check in them.

The real reason parity was added to the PCI bus is that customers
demand it.  We engineers understand its true value or lack of, but the
customers demand it even though they don't understand it.  But, as we
all know, customers are always right.  That is wrong, but as I have
said before, that is the way it is.  It is all politics.  On the other
hand, the spec could have satisfied that demand without making it
difficult for an FPGA implementation by pipelining parity by one clock
cycle.