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Re: Purposeful Parity control
1. Is there some reason why it is felt that the PCI bus is more
susceptible to single bit failures then the rest of the data paths in the
machine? How about verfication of hardware control lines (PCI included)?
are they less likely to fail? Maybe it could be argued that it is better
to have some detection capability rather than none. I have always
suspected that parity and EDC (error detection and correction) existed on
buses because of the possibility of single point upsets in memory devices
(specifically DRAM). Since the PCI bus does not connect directly to memory
chips, I would argue that the PCI device which interfaces to this type of
memory is the one who should implement the EDC/Parity algorithm.
2. If we are talking about the desktop, my suspicion is that the
likelihood of a serious system problem due to a software crash (either OS
or application) is orders of magnitude more likely than a PCI data bus
parity error. I think that the same argument might be made for most
embedded systems (except possibly those whose software has been tested very
rigorously (e.g. formal verification)).
Lame Brooks-G14738 <Brooks_Lame-G14738@email.mot.com> on 04/17/2001
To: "PCISIG List (E-mail)" <email@example.com>
cc: "'Dimiter Popoff'" <firstname.lastname@example.org>
Subject: Purposeful Parity control RE: PCI Politics (was RE: why Target
cannot change its mind)
> Why was the parity control necessary for a chip-to-chip bus?
For the same reason it's necessary in other reliable, high-speed data
transfer mechanisms - it is very easy for single bit errors to sneak in, be
they due to design margin, bad components, external influence, or whatever,
and without some bandwidth-efficient, cost-effective detection method, a
single bit error could easily run undetected for a while and worm its way
into causing system instability.